S29GL01GP
S29GL512P
S29GL256P
S29GL128P
8.6.3
Write Pulse “Glitch Protection”
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.6.4
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#.
The internal state machine is automatically reset to the read mode on power-up.
9. Power Conservation Modes
9.1
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device
enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC ± 0.3 V. The device requires standard
access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the
device draws active current until the operation is completed. ICC4 in “DC Characteristics” represents the standby current
specification
9.2
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when
addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and
always available to the system. ICC6 in Section 11.6 represents the automatic sleep mode current specification.
9.3
Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at
least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write
commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data
integrity.
When RESET# is held at VSS ± 0.3 V, the device draws ICC reset current (ICC5). If RESET# is held at VIL but not within VSS ± 0.3 V,
the standby current is greater.
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash memory, enabling the system
to read the boot-up firmware from the Flash memory.
9.4
Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. (With the
exception of RY/BY#.)
Document Number: 002-00886 Rev. *B
Page 44 of 83
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