PEB 2091
PEF 2091
Application Hints
The BAC bit together with the EOC-messages received from the LT control the S/G bit
and the upstream D-channel according to Table 49.
.
Table 49
Control Structure of the S/G Bit and of the D-Channel
BAC bit of last S/G bit
IOM®-2-frame 1 = stop
0 = go
D-channel upstream
0
reflects last received EOC
tied to "0"
message after falling edge after
delay TD1 (1.5 ms and two
EOC-frames)
1
1
set transparent with first "0" in
D-channel
D-Channel Request by the Terminal
Figure 95, page 256, illustrates the request for the HDLC-controller by the terminal. The
start state is BAC = 1 at DIN after TD1 has expired. That causes the S/G bit to be set to
the stop position.
BAC = 1 received on DIN sets the S/G bit on DOUT to the stop position (’1’) at the next
IOM®-2-frame. When the terminal requests access to the HDLC-controller in the ELIC®
it sets the BAC-bit at DIN of it’s IEC-Q to "0". That causes the D-channel data upstream
to be tied to "0" and the S/G-bit to be set to "1". The ELIC® receives the zeros and reacts
by assigning the HDLC-controller to this very terminal. This is indicated via the change
of C/I code downstream at the LT side resulting in the S/G bit to be set to "0" (’go’) after
delay TD1 (see below for the explanation of TD1 and TD2).
The IEC-Q will continue to send "0" upstream in the D-channel until the HDLC data
arrives at DIN. The HDLC-frame itself, marked by the first "0" in the D-channel will reset
the D-channel back to transparent. This allows to have arbitrary delays between the S/G
bit going to "0" and the D-channel being used without the risk of loosing the
HDLC-controller by sending an abort request consisting of all "1".
At the end of the HDLC-frame the BAC bit is reset to "1" again by the layer-2 controller
(e.g. SMARTLINK; ICC). This causes the S/G bit to be set to "1" in the next IOM®-2 frame
which stops a possible second HDLC-frame that could not be processed in the ELIC®
anymore.
TD1 and TD2
The delays TD1 and TD2 (see Figure 95, page 256) have the following reasons: TD2 is
caused by the 6ms interval in which an EOC message can be transmitted on the
Semiconductor Group
254
Data Sheet 01.99
INFINEON [ Infineon ]
