PEB 2091
PEF 2091
List of Figures
Page
Figure 83
Figure 84
Figure 85
Figure 86
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Figure 113
Figure 114
Figure 115
Figure 116
Figure 117
Figure 118
Figure 119
Figure 120
Figure 121
Figure 122
Figure 123
Figure 124
Figure 125
Serial Data Port of Pin PS2 in LT Modes. . . . . . . . . . . . . . . . . . . . . . .195
Sampling of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
State Machine Notation for S/G Bit Control . . . . . . . . . . . . . . . . . . . . .200
State Machine for S/G Bit Control (part 1) . . . . . . . . . . . . . . . . . . . . . .201
State Machine for S/G Bit Control (part 2) . . . . . . . . . . . . . . . . . . . . . .202
State Machine for S/G Bit Control (Part 3). . . . . . . . . . . . . . . . . . . . . .203
S/G Bit Status on Pin S/G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
Example: C/I-Channel Use (all data values hexadecimal). . . . . . . . . .232
Power Supply Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
U-Interface Hybrid Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Crystal Oscillator or External Clock Source . . . . . . . . . . . . . . . . . . . . .252
D-Channel Request by the Terminal . . . . . . . . . . . . . . . . . . . . . . . . . .256
EOC-Handling in Repeater Applications . . . . . . . . . . . . . . . . . . . . . . .257
Maintenance Bit Handling in Repeaters (Example) . . . . . . . . . . . . . . .258
Total Power Measurement Set-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . .260
Maximum Sinusoidal Ripple on Supply Voltage . . . . . . . . . . . . . . . .263
Test Condition for Maximum Input Current . . . . . . . . . . . . . . . . . . . . .264
U transceiver Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
Pulse Mask for a Single Positive Pulse . . . . . . . . . . . . . . . . . . . . . . . .267
Input/Output Wave form for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . .269
Siemens/Intel Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
Siemens/Intel Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
Siemens/Intel Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . .270
Siemens/Intel Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . .271
Motorola Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
Motorola Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
Motorola Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . .272
Serial µP Interface Mode Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
Serial µP Interface Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
IOM®-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
IOM®-2 Timing of IOM®-2 Interface (Detail) . . . . . . . . . . . . . . . . . . . .275
Dynamic Characteristics of Power Controller Write Access. . . . . . . . .277
Dynamic Characteristics of Power Controller Read Access . . . . . . . .278
Dynamic Characteristics of Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .279
UVD Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
Clock Requirements in LT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
Dynamic Characteristics of the Duty Cycle . . . . . . . . . . . . . . . . . . . . .282
Maximum Sinusoidal Input Jitter of Master Clock 15.36 MHz . . . . . . .282
Clock Requirements in NT-PBX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
Dynamic Characteristics of CLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
Dynamic Characteristics of Pin SG . . . . . . . . . . . . . . . . . . . . . . . . . . .286
Package Outline for P-LCC-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
Semiconductor Group
12
Data Sheet 01.99