Electrical Characteristics
The 1536-kHz clock (TE mode) and the 512-kHz clock (LT-T mode) are phase-locked to the
receive S signal, and derived using the internal DPLL and the 7.68 MHz ± 100 ppm crystal.
A phase tracking with respect to "S" is performed once in 250 µs. As a consequence of this
DPLL tracking, the "high" state of the 1536-kHz clock may be either reduced or extended by
one 7.68-MHz period (duty ratio 2:2 or 4:2 instead of 3:2) once every 250 µs. Since the other
signals are derived from this clock (TE mode), the "high" or "low" states may likewise be
reduced or extended by the same amount once every 250 µs.
The phase relationships of the clocks are shown in figure 101.
7.68 MHz
:
X1 3840 kHz
*
1536 kHz
*
Synchronous to receive S/T. Duty Ratio 3:2 Normally
768 kHz
512 kHz
ITD00876
Figure 101
Phase Relationships of ISAC®-S Clock Signals
The timing relationships between the clocks are specified in figure 98 and table 28.
Semiconductor Group
260
INFINEON [ Infineon ]
