AIROC™ Bluetooth® system on chip for automotive applications
Microprocessor unit
2.4
Power modes
The CYW89820 supports the following HW power modes:
• Active mode: Normal operating mode in which all peripherals are available and CPU is active
• Idle mode - CPU is paused: In this mode, the CPU is in “Wait for Interrupt” (WFI) and the HCLK, which is the high
frequency clock derived from the main crystal oscillator, is running at a lower clock speed. Other clocks are
active and the state of the entire chip is retained.
• Sleep mode: All systems clocks idle except for the LPO. The chip can wake up either after a programmed period
of time has expired or if an external event is received via one of the GPIOs. In this mode, CPU is in WFI and the
HCLK is not running. The PMU determines if the other clocks can be turned off and does accordingly. State of
the entire chip is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM
is retained.
• PDS (Power Down Sleep) mode: Radio powered down and digital core mostly powered down except for RAM,
registers, and some core logic. CYW89819 can wake up either after a programmed period of time has expired or
if an external event is received via one of the GPIOs.
• ePDS (extended PDS) mode: This is an extension of the PDS Mode. In this mode, only the main RAM and ePDS
control circuitry retains power. As in other modes, the CYW89819 can wake up either after a programmed period
or upon receiving an external event.
• HID-OFF (Deep Sleep) mode: Core, radio, and regulators powered down. Only the LHL IO domain is powered.
In this mode, the CYW89819 can be woken up either by an event on one of the GPIOs or after a certain amount
of time has expired. After wakeup, the part will go through full FW initialization although it will retain enough
information to determine that it came out of HID-OFF and the event that caused the wake up. LPO and RTC are
turned off in this mode. Either an internal LPO or an external input would provide a measure of time.
Transition between power modes is handled by the on-chip firmware with host/application involvement. In
general ePDS is the most power efficient mode for most active use cases. HID-OFF generally works for
non-connectable beacon type use cases with long advertisement intervals. Refer to the “Firmware” on page 21
section for more details.
2.5
Watchdog
CYW89820 includes an onboard watchdog with a period of approx. 4 seconds. The watchdog timer generates an
interrupt to the FW after 2 seconds of inactivity and resets the parts after 4 seconds.
2.6
Lockout functionality
The CYW89820 power up with JTAG and SWD access to flash and RAM is disabled. After reset, FW checks OCF for
the presence of a security lockout field. If present, FW leaves JTAG and SWD Flash and RAM access disabled and
also blocks any HCI commands from reading the raw contents of the RAM or Flash.
The security field can be programmed in the factory after all programming and testing has been done. Refer to
the ModusToolbox™ software documentation for details on how to enable this feature. This provides an
effective way of protecting against any tampering, dumping, probing or reverse engineering of OCF resident user
application. The only FW upgrade path in this scenario is the secure OTA update.
2.7
True random number generator
The CYW89820 includes a hardware TRNG. Applications can access the random number generator via the
firmware driver. Refer to the ModusToolbox™ software documentation for details.
Datasheet
11
002-25826 Rev. *G
2022-09-24
INFINEON [ Infineon ]
