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AN985BX 参数 Datasheet PDF下载

AN985BX图片预览
型号: AN985BX
PDF下载: 下载PDF文件 查看货源
内容描述: [LAN Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP128, GREEN, PLASTIC, LQFP-128]
分类和应用: 时钟局域网数据传输PC外围集成电路
文件页数/大小: 112 页 / 4450 K
品牌: INFINEON [ Infineon ]
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AN985B/BX  
Functional Descriptions  
Table 4  
Field  
Format  
Description  
Preamble  
A 7-byte field of (10101010b)  
A 1-byte field of (10101011b)  
A 6-byte field  
Start Frame Delimiter  
Destination Address  
Source Address  
Length/Type  
A 6-byte field  
A 2-byte field indicated the frame is in IEEE802.3  
format or Ethernet format.IEEE802.3 format: 0000H ~  
05DCH for Length field Ethernet format: 05DD ~ FFFFH  
for Type field  
Data  
CRC  
461) ~ 1500 bytes of data information  
A 32-bit cyclic redundant code for error detection  
1) If padding is disabled (TDES1 bit23), the data field may be shorter than 46 bytes.  
Transmit Data Encapsulation  
The differences between the encapsulation and a MAC frame while operating in the 100BASE-TX mode are listed  
as follow:  
1. The first byte of the preamble is replaced by the JK code according to the IEE802.3u, clause 24.  
2. After the CRC field of the MAC frame, the AN985B/BX inserts the TR code according to the IEE802.3u, clause  
24.  
Receive Data Decapsulation  
When operating in 100BASE-TX mode the AN985B/BX detects a JK code for a preamble as well as a TR code  
for the packet end. If a JK code is not detected, the AN985B/BX will abort this frame receiving and wait for a new  
JK code detection. If a TR code is not detected, the AN985B/BX will report a CRC error.  
Deferring  
The Inter-Frame Gap (IFG) time is divided into two parts:  
1. IFG1 time (64-bit time): If a carrier is detected on the medium during this time, the AN985B/BX will reset the  
IFG1 time counter and restart to monitor the channel for an idle again.  
2. IFG2 time (32-bit time): After counting the IFG2 time the AN985B/BX will access the channel even though a  
carrier has been sensed on the network.  
Collision Handling  
The scheduling of re-transmissions is determined by a controlled randomization process called “truncated binary  
exponential back-off”. At the end of enforcing a collision (jamming), the AN985B/BX delays before attempting to  
re-transmit the packet. The delay is an integer multiple of slot time. The number of slot times to delay before the  
nth re-transmission attempt is chosen as a uniform distributed integer r in the range:  
0 r < 2k, where k = min (n, 10)  
Data Sheet  
25  
Rev. 1.51, 2005-11-30  
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