AN985B/BX
Appendix
11
Appendix
11.1
MII Management Access Procedure
Read Management Data From Phyter
1. Write CSR9[18]=1 to let Mdio become input mode.
2. Write CSR9[16] according to the IEEE802.3u spec to generate the MII management clock.
3. Read CSR9[19] with reference the MII management clock.
Write Management Data From Phyter
1. Write CSR9[18]=1 to let Mdio become output mode.
2. Write CSR9[16] according to the IEEE802.3u spec to generate the MII management clock.
3. Write CSR9[19] with reference the MII management clock.
11.2
Debugging Purpose Registers: Offset FCH
MAC(HOME/PNA), MODE/SET FCH[2:0]=100B
MDC:bra11
TXEN:bra10
TXD[3:0]:bra[9:6]
TXER:bra5
MDIO:bra3
RXDV:brd4
CRS:bra2
RXD[2:0]:brd[3:0]
COL:bra1
RXER:bra0
RXCLK:brwe_
RXCLK:broe_
PHY MINITOR MODE/SET FCH[2:0]=110B
bra[16:0]=rxd[3:0], crs, col, rx_clk, rx_dv, rx_er, rx_clk,txd[3:0], tx_er, tx_en, mdi
brd[7:6]=mdo, mdc
PHY ONLY MODE/SET FCH[2:0]=001B
bra[16:9]=rxd[3:0], csr, col,rx_er, rx_dv
brd[7:0]=mdc, mdio, tx_er, tx_en, txd[3:0]
broez=rx_clk
brwez=tx_clk
11.3
EEPROM DATA TABLE
Data Sheet
109
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
