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ILC7082 参数 Datasheet PDF下载

ILC7082图片预览
型号: ILC7082
PDF下载: 下载PDF文件 查看货源
内容描述: 150MA SOT- 23超低噪声CMOS RF- LDO稳压器 [150MA SOT-23 ULTRA LOW NOISE CMOS RF-LDO REGULATOR]
分类和应用: 稳压器
文件页数/大小: 16 页 / 334 K
品牌: IMPALA [ Impala Linear Corporation ]
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150mA SOT-23 Ultra Low Noise CMOS RF-LDO™ Regulator  
However, being aware of these current flows, there is also  
another potential source of induced voltage noise from the  
resistance inherent in the PCB trace. Figure 6 shows where  
the additive resistance of the PCB can manifest itself. Again  
these resistances may be very small, but a summation of  
several currents can develop detectable voltage ripple and  
will be amplified by the LDO. Particularly the accumulation  
of current flows in the ground plane can develop significant  
voltages unless care is taken. With a degree of care, the  
ILC7082 will yield outstanding performance.  
Printed Circuit Board Layout Guidelines  
As was mentioned in the previous section, to take full  
Figure 7: Effects of poor circuit layout  
advantage of any high performance LDO regulator requires  
paying careful attention to grounding and printed circuit  
board (PCB) layout.  
Figure 8 shows an optimum schematic. In this schematic,  
high output surge current has little effect on the ground cur-  
rent and noise bypass current return of the LDO regulator.  
Note that the key difference here is that COUT and CNOISE are  
directly connected to the LDO regulator’s ground pin. The  
LDO is then separately connected to the main ground plane  
and returned to a single point system ground.  
IOUT  
VOUT  
RPCB  
ESR  
RPCB  
I1  
COUT  
SOT-23-5  
5
1
4
3
CNOISE  
ILC7082  
The layout of the LDO and its external components are also  
based on some simple rules to minimize EMI and output  
voltage ripple.  
VIN  
CIN  
2
RPCB  
RPCB  
ON  
OFF  
Figure 6: Inherent PCB resistance  
Figure 7 shows the effects of poor grounding and PCB lay-  
out magnified by the ESR and PCB resistances and the  
accumulation of current flows.  
Note thatparticularly during high output load current, the  
LDO regulator’s ground pin and the ground return for COUT  
and CNOISE are not at the same potential as the system  
ground. This is due to high frequency impedance caused by  
PCB’s trace inductance and DC resistance. The current  
loop between COUT, CNOISE and the LDO regulator’s ground  
pin will degrade performance of the LDO.  
Impala Linear Corporation  
(408) 574-3939  
ILC7082 1.3  
www.impalalinear.com  
April 1999  
8