0.5A, 300kHz, SO-8 PWM/PFM Step Down Converter with Shutdown
To pin 8
EXT1
V
I N
S/D
*C
I N
SD1
1
+
2
3
4
8
V
OU T
L
6
5
ILC6377
(TOP VIE W)
7
6
5
+
C
F B
R
FB1
R
FB2
V
O UT
C
L
R
FB 1
+ R
F B2
≤
2MΩ
1
C
F B
chosen so that
1kHz
<
-----------------------------------------------------
<
20kHz
2
× π ×
CF B
×
RFB1
C
SS
Fig. 2: 1Amp output current application using
application
Fig.2 1Amp output current
external MOSFET
using external MOSFET
The EXT1 and EXT2 pins are provided so as to drive
external transistors; thus allowing design flexibility.
The EXT output drive signal has the same timing as
the gate drive to the internal P-channel MOSFET i.e.
EXT output is low as long as the internal MOSFET is
on. Both EXT1 and EXT2 pins are capable of driving
1000pF gate capacitance. For example, a high out-
put current application circuit using an external P-
channel MOSFET is shown in figure 2.
Fig. 4: Adjustable output using
ILC6377SO-Adj
Fig.4 Adjustable output using
ILC6377SO-Adj
(Note: rest
( Note : rest
of circuit is same as figure
Fig.1 )
of circuit is same as
1)
Adjustable Output ( ILC6377SO-Adj )
For adjustable output voltage ILC6377SO-Adj should be
used. All connections to the ILC6377SO-Adj are the same
as ILC6377SO-XX, except for the feedback voltage divider
network shown in figure 4. The output voltage, V
OUT
, can be
calculated from the following equation:
V
OUT
= V
FB
( 1 + R
FB1
/R
FB2
),
where V
FB
is approximately 1V and
RFB1 + RFB2 < 2MΩ
The feedback compensation capacitor should be chosen
such that the pole frequency f is between 1kHz and 20kHz:
1
8
C
BST
2200pF
SD1
MA729
Schottky
2
3
4
ILC6377
(TOP VI EW)
7
6
5
1kHz<
Voltage between V
IN
and P_BST
between Vin and
must be less than 10V.
1
2 x
Π
X CFB X RFB1
<20kHz
Fig.
3. P-Channel Negative
Figure
3: P-Channel Negative
P-Channel Boost Circuit
The ILC6377 includes a unique P-Channel MOSFET
architecture with built-in charge pump to maintain low
on-resistance even at low input voltages. As shown in
figure 3, a 2200pF ceramic capacitor and a schottky
diode ( MA729 or equivalent ) allows the gate voltage
of the internal P-Channel MOSFET to be driven neg-
ative; thus reducing the switch on-resistance. This
technique can be employed to increase efficiency at
low input voltages and high output currents.
Note that the voltage between V
IN
and P_BST should not
exceed 10V, otherwise damage to the device may occur.
For high input voltage applications the schottky diode
should be replaced by a low voltage zener diode so that the
P_BST pin is clamped to a safe negative voltage.
The pole frequency should generally be set at 5kHz. The
value of C
FB
calculated from the above equation may
require some adjustment depending on the output inductor
( L ) and output capacitor ( CL ) values chosen.
Example for 3V output :
RFB1 = 400kΩ
RFB2 = 200kΩ
CFB = 100pF
PC Board Layout
As with all switching DC-DC converter designs, good PC
board layout is critical for optimum performance.
The heavy
lines indicated in figure 1 schematic should be wide
printed circuit board traces and should be kept as short
as is practical.
A large ground plane with as much copper
area as is allowable should be used. All external compo-
nents should be mounted as close to the IC as possible. For
ILC6377SO-Adj, the feedback resistors and their associat-
ed wiring should be kept away from the inductor location
and the vicinity of inductive flux.
Impala Linear Corporation
ILC6377 1.3
(408) 574-3939
www.impalalinear.com
June 1999
6
IMPALA [ Impala Linear Corporation ]
