SOT-23 Power Supply reset Monitor
Functional Description
The following designators
1~6
refer to the timing diagram below.
1.
While the input voltage (V
IN
) is higher than the detect volt-
age (V
DF
), the V
OUT
output pin is at high impedance state.
2.
When the input VIN voltage falls lower than V
DF
, V
OUT
drops near to ground voltage
3.
If the input voltage further decreases below the mini-
mum operating voltage (V
MIN
), the V
OUT
output becomes
unstable. In this condition, if the V
OUT
pin is pulled up,
V
OUT
indicates the V
IN
voltage.
4.
During an increase of the input voltage from the V
SS
voltage, V
OUT
is not stable in the voltage below the V
MIN
.
Exceeding that level, the output stays at the ground level
(V
SS
) between the minimum operating voltage (V
MIN
) and
the detect release voltage (V
DR
).
5.
If the input voltage increases more than V
DR
, then the
V
OUT
output pin is at high impedance state.
6.
The difference between VDR and VDF is the hysteresis
in the system.
Timing Diagram
INPUT VOLTAGE (V
IN
)
DETECT RELEASE VOLTAGE (V
DR
)
6
DETECT FAIL VOLTAGE (V
DF
)
MINIMUM OPERATING VOLTAGE (V
MIN
)
GROUND VOLTAGE (V
SS
)
OUTPUT VOLTAGE (V
OUT
)
GROUND VOLTAGE (V
SS
)
1
2
3
4
5
Impala Linear Corporation
ILC5061 1.7
(408) 574-3939
www.impalalinear.com
June 1999
3
IMPALA [ Impala Linear Corporation ]
