SOT-23 Power Supply reset Monitor
Functional Description
The following designators 1~6 refer to the timing diagram below. 4. During an increase of the input voltage from the VSS
voltage, VOUT is not stable in the voltage below the VMIN
.
1. While the input voltage (VIN) is higher than the detect volt-
Exceeding that level, the output stays at the ground level
age (VDF), the VOUT output pin is at high impedance state.
(VSS) between the minimum operating voltage (VMIN) and
the detect release voltage (VDR).
2. When the input VIN voltage falls lower than VDF, VOUT
drops near to ground voltage
5. If the input voltage increases more than VDR, then the
VOUT output pin is at high impedance state.
3. If the input voltage further decreases below the mini-
mum operating voltage (VMIN), the VOUT output becomes
unstable. In this condition, if the VOUT pin is pulled up,
VOUT indicates the VIN voltage.
6. The difference between VDR and VDF is the hysteresis
in the system.
Timing Diagram
INPUT VOLTAGE (VIN)
DETECT RELEASE VOLTAGE (VDR
)
6
DETECT FAIL VOLTAGE (VDF
)
MINIMUM OPERATING VOLTAGE (VMIN
GROUND VOLTAGE (VSS
)
)
OUTPUT VOLTAGE (VOUT
)
GROUND VOLTAGE (VSS
)
4
1
2
3
5
Impala Linear Corporation
ILC5061 1.7
www.impalalinear.com
(408) 574-3939
June 1999
3
IMPALA [ Impala Linear Corporation ]
