IMP8 1 1 , IMP8 1 2
Detailed Description
Reset Timing and Manual Reset (MR)
The reset signal is asserted–LOW for the IMP811 and HIGH for
the IMP812 – when the V
CC
signal falls below the threshold trip
voltage and remains asserted for 140ms minimum after the V
CC
has risen above the threshold.
A logic low on MR asserts RESET LOW on the IMP811 and HIGH
on the IMP812. MR is internally pulled high through a 20kΩ
resistor and can be driven by TTL/CMOS gates or with open
collector/drain outputs. MR can be left open if not used.
MR may be connected to a normally-open switch connected to
ground without an external debounce circuit.
For added noise rejection, a 0.1µF capacitor from MR to Ground
can be added.
5V
V
CC
0V
V
TH
Active Reset
Timeout Period
140ms
minimum
5V
MR
0V
Active Reset
Timeout Period
5V
RESET
0V
5V
RESET
0V
811/12_03.eps
IMP811
IMP812
Figure 1. Reset Timing and Manual Reset (MR)
©
1999 IMP, Inc.
408-432-9100/www.impweb.com
5
IMP [ IMP, INC ]
