IMP690A , 692A , 802L, 802M, 805L
Application Information
Reset Output
It is important to initialize a microprocessor to a known state in
response to specific events that could create code execution errors
and “lock-up”. The reset output of these supervisory circuits send
a reset pulse to the microprocessor in response to power-up,
power-down/power-loss or a watchdog time-out. The reset pulse
width, t
RS
, is typically around 200ms and is LOW for the
IMP690A, IMP692A, IMP802 and HIGH for the IMP805L.
Power-up reset occurs when a rising V
CC
reaches the reset thresh-
old, V
RT
, forcing a reset condition in which the reset output is
asserted in the appropriate logic state for the duration of t
RS
.
Figure 2
shows the reset pin timing.
Power-loss or “brown-out” reset occurs when V
CC
dips below the
reset threshold resulting in a reset assertion for the duration of t
RS
.
The reset signal remains asserted as long as V
CC
is between V
RT
and 1.1V, the lowest V
CC
for which these devices can provide a
guaranteed logic-low output. To ensure logic inputs connected to
the IMP690A/692A/802 RESET pin are in a known state when
V
CC
is under 1.1V, a 100kΩ pull-down resistor at RESET is needed:
the logic-high IMP805L will need a pull-up resistor to V
CC
.
A Watchdog time-out reset occurs when a logic “1” or logic “0” is
continuously applied to the WDI pin for more than 1.6 seconds.
After the duration of the reset interval, the watchdog timer starts
a new 1.6 second timing interval; the microprocessor must service
the watchdog input by changing states or by floating the WDI pin
before this interval is finished. If the WDI pin is held either HIGH
or LOW, a reset pulse will be triggered every 1.8 seconds (the 1.6
second timing interval plus the reset pulse width t
RS
).
Microprocessor Interface.
The IMP690 has logic-LOW RESET output while the IMP805 has
an inverted logic-HIGH RESET output. Microprocessors with bi-
directional reset pins (69HC11 for example) can pose a problem
when the supervisory circuit and the microprocessor output pins
attempt to go to opposite logic states. The problem can be
resolved by placing a 4.7kΩ resistor between the RESET output
and the microprocessor reset pin. This is shown in
Figure 3.
Since
the series resistor limits drive capabilities, the reset signal to other
devices should be buffered.
+5V
V
CC
+0V
+5V
V
OUT
+0V
+5V
RESET
+0V
+5V
(RESET)
+0V
+5V
PFO
+0V
( ) IMP805L
V
BATT
= PFI = 3.0V
I
OUT
= 0mA
690A_04.eps
3.0V
t
RS
3.0V
Figure 2. Timing Diagram
V
BATT
V
CC
+
8
2
Battery-Switchover
Circuit
Reset
Generator
+
1
7
V
OUT
RESET
(RESET)
Buffered RESET to Other System Components
1.25V
3.5V
6
WDI
+
+
+
+
Watchdog
Timer
V
CC
1.25V
+
+
V
CC
4.7k
0.8V
4
PFI
5
PFO
RESET
IMP690A
GND
RESET
IMP690A, IMP692A, IMP802L, IMP802M,
IMP805L
( ) IMP805L
3
GND
690A_03.eps
GND
690A_05.eps
Figure 1. Block Diagram
Figure 3. Interfacing with bi-directional microprocessor
reset inputs
5
IMP [ IMP, INC ]
