IMP706P/R/S/T/J, IMP708R/S/T/J
Application Information
Bi-directional Reset Pin Interfacing
The IMP706/8 can interface with µP/µC bi-directional reset pins
by connecting a 4.7kΩ resistor in series with the RESET output
and the µP/µC bi-directional reset pin.
Ensuring That RESET is Valid Down to VCC = 0V
When VCC falls below 1.2V, the IMP706R/S/T/J and
IMP708R/S/T/J RESET reset outputs no longer pull down; it
becomes indeterminate. To avoid the possibility that stray charges
could build up and force RESET to the wrong state, a pull-down
resistor should be connected to the RESET pin, thus draining such
charges to ground. The resistor value is not critical. A 100kΩ resis-
tor will pull RESET to ground without loading it.
BUF
Buffered
RESET
Monitoring Voltages Other Than VCC
V
The IMP706/708 can monitor voltages other than VCC using the
Power Fail circuitry. If a resistive divider is connected from the
voltage to be monitored to the PFI input, the PFO (output) will go
LOW if the divider voltage goes below its 1.25V reference. Should
hysteresis be desired, connect a resistor (equal to approximately
10 times the sum of the two resistors in the divider) between the
PFI and PFO pins. A capacitor between PFI and GND will reduce
circuit sensitivity to input high frequency noise. If it is desired to
assert a reset in addition to the PFO flag, this may be achieved by
connecting the PFO output to MR.
CC
IMP70x
Supply
Voltage
C or
P
4.7k
RESET
Input
RESET
GND
GND
Bi-directional I/O Pin
(Example: 68HC11)
706P_06.eps
Package Dimensions
MicroSO (8-Pin)
a
Inches
Min
Millimeters
Min Max
MicroSO (8-Pin)*
Max
A
A1
A2
b
–––––
0.0020
0.0295
0.0098
0.0051
0.1142
0.0433
0.0059
0.0374
0.0157
0.0091
0.1220
––––
1.10
0.15
0.95
0.40
0.23
3.10
0.050
0.75
0.25
0.13
2.90
E1
E
C
D
L
e
0.0256 BSC
0.193 BSC
0.65 BSC
4.90 BSC
D
E
C
A2
E1
L
0.1142
0.1220
0.0276
6°
2.90
0.40
0°
3.10
0.70
6°
0.0157
A
a
0°
0.10mm
0.004in
e
MicroSO (8-Pin).eps
706P_t02a.at3
* JEDEC Drawing MO-187AA
A1
b
©
1999 IMP, Inc.
408-432-9100/www.impweb.com
7
IMP [ IMP, INC ]
