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IMP1832S 参数 Datasheet PDF下载

IMP1832S图片预览
型号: IMP1832S
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3VレP电源增刊监控和复位电路 [3.3V レP Power Suppl Monitor and Reset Circuit]
分类和应用: 复位电路监控
文件页数/大小: 7 页 / 111 K
品牌: IMP [ IMP, INC ]
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IMP1832  
Application Information  
Supply Voltage Monitor  
The IMP1832 monitors the microprocessor or microcontroller On power-down, once VCC falls below the reset threshold RESET  
power supply and issues reset signals, both active HIGH and stays LOW and is guaranteed to be 0.4V or less until VCC drops  
active LOW, that halt processor operation whenever the power below 1.2V. The active HIGH reset signal is valid down to a VCC  
supply voltage levels are outside a predetermined tolerance.  
level of 1.2V also.  
Tolerance levels are set with the TOL pin.  
TRIP Point Voltage (V)  
Tolerance  
Select  
RESET and RESET signals are generated at the last moment of a  
valid VCC signal. On power-up, both reset signals are active for a  
minimum of 250ms after the supply has returned to intolerance  
level. This allows the power supply and monitored processor to  
stabilize before instruction execution is allowed to begin.  
Tolerance  
20%  
Min  
Nominal  
2.55  
Max  
TOL = VCC  
TOL = GND  
2.47  
2.80  
2.64  
10%  
2.88  
2.97  
1832 t02.eps  
Trip Point Tolerance Selection  
Manual Reset Operation  
Push-button switch input, PBRST, allows the user to override the  
internal trip point detection circuits and issue reset signals. The  
pushbutton input is debounced and is pulled HIGH through an  
internal 40kresistor.  
With TOL connected to VCC, RESET and RESET become active  
whenever VCC falls below 2.64V. RESET and RESET become active  
when VCC falls below 2.98V if TOL is connected to ground.  
After VCC has risen above the trip point set by TOL, RESET and  
RESET remain active for a minimum time period of 250ms.  
When PBRST is held LOW for the minimum time tPB , both resets  
become active and remain active for a minimum time period of  
250ms after PBRST returns HIGH.  
tR  
The debounced input is guaranteed to recognize pulses greater  
than 20ms. No external pull-up resistor is required, since PBRST  
is pulled HIGH by an internal 40kresistor.  
VCCTP(MAX)  
VCCTP  
VCCTP(MIN)  
The PBRST can be driven from a TTL or CMOS logic line or short-  
ed to ground with a mechanical switch.  
VCC  
tRPU  
RESET  
tPB  
PBRST  
VOH  
tPDLY  
V
IH  
V
IL  
tRST  
VOL  
RESET  
1832_04.eps  
RESET  
Figure 1. Timing Diagram: Power Up  
VOH  
VOL  
RESET  
1832_07.eps  
tF  
Figure 3. Timing Diagram: Pushbutton Reset  
VCC  
VCCTP(MAX)  
VCCTP  
Supply  
Voltage  
VCCTP(MIN)  
IMP1832  
8
7
1
2
3
4
PBRST  
TD  
VCC  
ST  
tRPD  
RESET  
µP  
6
5
TOL  
RESET  
GND RESET  
RESET  
VOH  
VOL  
1832_05.eps  
RESET  
1832_03.eps  
Figure 4. Application Circuit: Pushbutton Reset  
Figure 2. Timing Diagram: Power Down  
408-432-9100/ www.impweb.com  
© 1999 IMP, Inc.  
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