IMP16C552
Mnemonic
Pin
type
IN
Pin#
description
RESET
39
Master reset: When this input is low it clears all the register(except the
Receiver Buffer, Transfer Holding and Divisor Latches) and the control
logic of the both channels and parallel port the states of various output
signals are affected by an active RESET input (refer to table 1) .this
input is buffered with a TTL-compatible schmitt trigger with 0.5v
hysteresis.
Serial inputs :Serial data input from the communication link such as
peripheral device , MODE or data set to the associated serial channel
DSR0*,
DSR1*
IN
28.13
Clear To Send: When low this pin indicates that the MODEM or data
set is ready to exchange data The CTS0(1)*.signal is a MODEM status
input whose conditions can be tested by the CPU reading bit4(CTS)of
the MODEM Status Register Bit4 is the complement of the CTS0(1)
signal Bit 0 (DCTS )of the MODEM status register indicates whether the
CTS(1)* input has changed state since the previous reading of the
modem status register CTS0(1)* has no the Transmitter
Note: whenever the CTS bit of the MODEM status register changes
state an interrupt is generated if the MODEM status interrupt is enabled
IN
31.5
Data Set Ready :When low this pin indicates that modem or data set is
ready to establish the communication link with the UART the DSR0(1)
signal is a MODEM status input whose condition can be tested by the
CPU reading bit 5 (DSR)of the MODEM status register bit 5 is the
complement of the DSR0(1)* signal. bit 1 (DDSR) of the MODEM Status
Register Indicates whether the DSR0(1)* input has changed state since
the previous reading of the MODEM Status Register DSR0(1)* has no
the transmitter
Note: Whenever the DSR bit of the MODEM Status Register changes
state, an interrupt is generated if the MODEM status interrupt is enable
IN
29.8
Receiver Line Signal Detect: When low ,this pin indicates that the data
canter has been detected by the MODEM or data set The RLSD0(1)*
signal is a MODEM status input whose condition can be tested by the
CPU reading bit 7(RLSD)of the MODEM Status Register Bit 7 is the
complement of the RLSD0(1)* signal. Bit 3 (DRLSD) of the MODEM
Status Register indicates whether the RLSD0(1)* input has changed
state since the previous reading of the MODEM Status Register
RLSD0(1)* has no effect on the receive
Note: whenever the RLSD bit of the MODE status register changes state
on interrupt is generated if the MODEM status interrupt is enable
IN
30.6
Ring indicator : when low this pin indicates that a telephone ringing
signal has been received by the MODEM or data set The RI0(1)* signal
is a MODEM status input whose condition can be tested by the CPU
reading bit 6 (RI) of the MODEM Status Register Bit 6 is the
complement of the RI0(1) signal Bit2 (TERI) of MODEM Status
Register indicates whether the RI0(1) input signal has changed from a
low to a high state since the previous reading of the MODEM Status
Register.
Note: whenever the RI bit of the MODEM Status Register changes from
a low to a high state an interrupt is generated if the MODEM status
interrupt is enabled
VCC
VSS
IN
23.40.64
SIN0 STS1
IN
41.62
DSR0*
DSR1*
RLSD0*
RISD1*
RI0* RI1*
+5V supply
2.7.27
43.54
Ground
5
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