IMP1 232LP/LPS
Application Information
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is
“hung-up”. Through the time delay input, TD, three watchdog
time-out periods are selectable: 150ms, 610ms and 1,200ms. If the
strobe input, ST, is not strobed LOW prior to timeout, reset signals
become active. On power-up or after the supply voltage returns to
an in-tolerance condition, the reset signal remains active for
250ms minimum, allowing the power supply and system micro-
processor to stabilize.
ST Pulses as short as 20ns can be detected.
Valid
Strobe
Valid
Strobe
Invalid
Strobe
A HIGH-to-LOW ST signal transition must be regularly issued
no later than the minimum time-out period defined by the state of
the TD signal. This guarantees the watchdog timer does not
time-out.
Timeouts periods of approximately 150ms, 610ms or 1,200ms are
selected through the TD pin.
TD Voltage Level
GND
Floating
V
CC
Watchdog Time-Out Period (ms)
Min
62.5
250
500
Nominal
150
610
1200
Max
250
1000
2000
1232_t03.eps
ST
t
ST
t
RST
RESET
t
TD
(Min)
t
TD
(Max)
1232_09.eps
The watchdog timer cannot be disabled. It must be strobed with a
high-to-low transition to avoid a watchdog timeout.
Note: ST is ignored whenever a reset is active.
Figure 5. Timing Diagram: Strobe Input
5V
IMP1232LP/LPS
1
2
3
4
PBRST
TD
TOL
GND
V
CC
ST
RESET
RESET
8
7
6
5
1232_07.eps
MREQ
10kΩ
µP
RESET
Address
Bus
Decoder
Figure 6. Application Circuit: Watchdog Timer
©
1999 IMP, Inc.
408-432-9100/www.impweb.com
5
IMP [ IMP, INC ]
