TECHNICAL DATA
IN74HC74A
Dual D Flip-Flop with Set and Reset
The IN74HC74A is identical in pinout to the LS/ALS74. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LS/ALSTTL outputs.
This device consists of two D flip-flops with individual Set, Reset, and
Clock inputs. Information at a D-input is transferred to the corresponding Q
output on the next positive going edge of the clock input. Both Q and Q
outputs are available from each flip-flop. The Set and Reset inputs are
asynchronous.
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Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
ORDERING INFORMATION
IN74HC74AN Plastic
IN74HC74AD SOIC
TA = -55° to 125° C for all packages
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock
Outputs
Set
L
Reset
H
Data
X
Q
Q
X
X
X
H
L
H*
H
L
L
H
H*
L
H
L
L
X
L
X
H
H
H
H
H
H
H
PIN 14 =VCC
PIN 7 = GND
H
L
H
H
L
X
No Change
No Change
No Change
H
H
X
H
X
*Both outputs will remain high as long as Set
and Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
X = don’t care
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
