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IN74HCT574A 参数 Datasheet PDF下载

IN74HCT574A图片预览
型号: IN74HCT574A
PDF下载: 下载PDF文件 查看货源
内容描述: 八路三态同相D触发器高性能硅栅CMOS [Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS]
分类和应用: 触发器
文件页数/大小: 6 页 / 304 K
品牌: IKSEMICON [ IK SEMICON CO., LTD ]
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IN74HCT574A  
AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)  
Guaranteed Limit  
Symbol  
Parameter  
Unit  
25 °C  
to  
85°C  
125°C  
-55°C  
fmax  
Maximum Clock Frequency (50% Duty Cycle)  
(Figures 1 and 4)  
30  
30  
28  
28  
12  
24  
38  
35  
35  
15  
20  
45  
42  
42  
18  
MHz  
ns  
tPLH, tPHL Maximum Propagation Delay, Clock to Q  
(Figures 1 and 4)  
tPLZ, tPHZ Maximum Propagation Delay, Output Enable to  
Q (Figures 2 and 5)  
ns  
tPZH, tPZL Maximum Propagation Delay, Output Enable to  
Q (Figures 2 and 5)  
ns  
tTLH, tTHL Maximum Output Transition Time, Any Output  
(Figures 1 and 4)  
ns  
CIN  
Maximum Input Capacitance  
10  
15  
10  
15  
10  
15  
pF  
pF  
COUT  
Maximum Three-State Output Capacitance  
(Output in High-Impedance State)  
Power Dissipation Capacitance (Per Flip-Flop)  
Typical @25°C,VCC=5.0 V  
CPD  
Used to determine the no-load dynamic power  
consumption:  
58  
pF  
PD=CPDVCC2f+ICCVCC  
TIMING REQUIREMENTS (VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)  
Guaranteed Limit  
Symbol  
Parameter  
Unit  
25 °C to  
-55°C  
85°C  
125°C  
15  
tSU  
th  
Minimum Setup Time, Data to  
Clock (Figure 3)  
10  
13  
ns  
ns  
ns  
ns  
Minimum Hold Time, Clock  
to Data (Figure 3)  
5
5
5
tw  
Minimum Pulse Width, Clock  
(Figure 1)  
15  
500  
19  
22  
tr, tf  
Maximum Input Rise and Fall  
Times (Figure 1)  
500  
500  
Rev. 00