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IN74HCT273A 参数 Datasheet PDF下载

IN74HCT273A图片预览
型号: IN74HCT273A
PDF下载: 下载PDF文件 查看货源
内容描述: 八路D触发器与普通时钟和复位高性能硅栅CMOS [Octal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS]
分类和应用: 触发器时钟
文件页数/大小: 6 页 / 295 K
品牌: IKSEMICON [ IK SEMICON CO., LTD ]
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IN74HCT273A  
AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)  
Guaranteed Limit  
Symbol  
Parameter  
Unit  
25 °C  
to  
85°C  
125°C  
-55°C  
fmax  
Maximum Clock Frequency (50% Duty Cycle)  
(Figures 1 and 4)  
30  
25  
25  
18  
10  
24  
28  
28  
20  
10  
20  
35  
35  
22  
10  
MHz  
ns  
tPLH, tPHL Maximum Propagation Delay, Clock to Q  
(Figures 1 and 4)  
tPHL  
Maximum Propagation Delay , Reset to Q  
(Figures 2 and 4)  
ns  
tTLH, tTHL Maximum Output Transition Time, Any Output  
(Figures 1 and 4)  
ns  
CIN  
Maximum Input Capacitance  
pF  
Power Dissipation Capacitance (Per Gate)  
Typical @25°C,VCC=5.0 V  
CPD  
Used to determine the no-load dynamic power  
consumption:  
30  
pF  
PD=CPDVCC2f+ICCVCC  
TIMING REQUIREMENTS (VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)  
Guaranteed Limit  
Symbol  
Parameter  
Unit  
25 °C to  
-55°C  
85°C  
125°C  
15  
tSU  
th  
Minimum Setup Time, Data to  
Clock (Figure 3)  
10  
3.0  
5.0  
12  
ns  
ns  
ns  
Minimum Hold Time, Clock  
to Data (Figure 3)  
3.0  
3.0  
trec  
Minimum Recovery Time,  
Reset Inactive to Clock  
(Figure 2)  
5.0  
5.0  
tw  
tw  
Minimum Pulse Width, Clock  
(Figure 1)  
12  
12  
15  
15  
18  
18  
ns  
ns  
ns  
Minimum Pulse Width, Reset  
(Figure 2)  
tr, tf  
Maximum Input Rise and Fall  
Times (Figure 1)  
500  
500  
500  
Rev. 00