TECHNICAL DATA
IN74HC75A
Dual 2-Bit Transparent Latch
High-Performance Silicon-Gate CMOS
The IN74HC75A is identical in pinout to the LS/ALS75. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
This device consists of two independent 2-bit transparent latches and
can be used as temporary storage for binary information between
processing units and input/output or indicator units. Each latch stores the
input data while Latch Enable is at a logic low. The outputs follow the
data inputs when Latch Enable is at a logic high.
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Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
ORDERING INFORMATION
IN74HC75AN Plastic
IN74HC75AD SOIC
TA = -55° to 125° C for all packages
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
PIN 5=VCC
PIN 12 = GND
Inputs
Latch
Outputs
D
Q
Q
Enable
L
H
X
H
H
L
L
H
H
L
Q0
Q0
X = Don’t Care
Q0 = latched data
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
