TECHNICAL DATA
IN74HC573A
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
N SUFFIX
PLASTIC DIP
The IN74HC573A is identical in pinout to the LS/ALS573. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when LE is high. When LE goes low, data meeting the
setup and hold time becomes latched.
20
1
DW SUFFIX
SOIC
20
1
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
ORDERING INFORMATION
IN74HC573AN
IN74HC573ADW
Plastic DIP
SOIC
High Noise Immunity Characteristic of CMOS Devices
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
OE
D0
1
20
19
18
17
16
15
14
13
12
11
V
CC
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
19
D1
3
2
Q0
Q1
Q2
Q3
D0
18
17
16
15
14
13
12
3
4
5
D2
4
D1
D2
5
D3
D3
D4
D4
6
DATA
INPUTS
NONINVERTING
OUTPUTS
6
Q4
Q5
D5
7
7
8
D5
D6
D7
D6
8
Q6
Q7
9
D7
9
10
GND
11
LE
FUNCTION TABLE
1
OE
Inputs
Output
OE
L
LE
H
D
H
L
Q
PIN 20=VCC
PIN 10 = GND
H
L
H
L
no change
Z
L
L
X
X
H
X
H= high level
L = low level
X = don’t care
Z = high impedance
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
