TECHNICAL DATA
IN74HC373A
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
The IN74HC373A is identical in pinout to the LS/ALS373. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes low,
data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the high-
impedance state. Thus, data may be latched even when the outputs are not
enabled.
ORDERING INFORMATION
IN74HC373AN Plastic
IN74HC373ADW SOIC
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•
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Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
TA = -55° to 125° C for all packages
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Latch
Enable Enable
Output
Q
PIN 20=VCC
PIN 10 = GND
Output
D
L
L
L
H
H
H
L
H
L
H
L
No Change
Z
X
X
X
X = Don’t Care
Z = High Impedance
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
