TECHNICAL DATA
IN74HC166A
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The IN74HC166A is identical in pinout to the LS/ALS166. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
This device is a parallel-in or serial-in, serial-out shift register with
gated clock inputs and an overriding clear input. The shift/load input
establishes the parallel-in or serial-in mode. When high, this input enables
the serial data input and couples the eight flip-flops for serial shifting with
each clock pulse. Synchronous loading occurs on the next clock pulse
when this is low and the parallel data inputs are enabled. Serial data flow
is inhibited during parallel loading. Clocking is done on the low-to-high
level edge of the clock pulse via a two input positive NOR gate, which
permits one input to be used as a clock enable or clock inhibit function.
Clocking is inhibited when either of the clock inputs are held high,
holding either input low enables the other clock input. This will allow the
system clock to be free running and the register stopped on command
with the other clock input. A change from low-to-high on the clock
inhibit input should only be done when the clock input is high. A
buffered direct clear input overrides all other inputs, including the clock,
andsets all flip-flop to zero.
ORDERING INFORMATION
IN74HC166AN Plastic
IN74HC166AD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
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Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
