TECHNICAL DATA
IN74HC112A
Dual J-K Flip-Flop
with Set and Reset
High-Performance Silicon-Gate CMOS
The IN74HC112A is identical in pinout to the LS/ALS112. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
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•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
ORDERING INFORMATION
IN74HC112AN Plastic
IN74HC112AD SOIC
TA = -55° to 125° C for all packages
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock
Outputs
Set
Reset
H
J
K
X
X
X
L
Q
Q
L
L
H
L
X
X
X
X
X
X
L
H
L
L*
L
H
L*
L
H
H
H
H
H
H
H
H
No Change
H
L
H
L
L
H
L
H
H
H
X
X
X
H
H
H
X
X
X
Toggle
H
L
No Change
No Change
No Change
H
H
PIN 16=VCC
PIN 8 = GND
H
* Both output will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
