TECHNICAL DATA
IN74AC109
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
The IN74AC109 is identical in pinout to the LS/ALS109,HC/HCT109.
The device inputs are compatible with standard CMOS outputs, with
pullup resistors, they are compatible with LS/ALS outputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs with
the next low-to-high transition of the clock. Both Q to Q outputs are
available from each flip-flop.
ORDERING INFORMATION
IN74AC109N Plastic
IN74AC109D SOIC
TA = -40° to 85° C for all packages
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Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 μA; 0.1 μA @ 25°C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock
Outputs
Set Reset
J
K
X
X
X
L
Q
Q
L
H
L
H
L
X
X
X
X
X
X
L
H
L
L
H
L
H*
H*
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
Toggle
No Change
H
H
X
H
X
H
L
L
No Change
PIN 16=VCC
PIN 8 = GND
X = Don’t care
*Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
