IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
PERFORMANCE OVERVIEW
THERMAL CONSIDERATIONS
The IDT79R3051 family achieves a very high level of
performance. This performance is based on:
The IDT79R3051 family utilizes special packaging tech-
niques to improve the thermal properties of high-speed pro-
• An efficient execution engine. The CPU performs ALU cessors. Thus, all versions of the IDT79R3051 family are
operations and store operations at a single cycle rate, and packaged in cavity-down packaging.
has an effective load time of 1.3 cycles, and a branch
The lowest cost members of the family use a standard
execution rate of 1.5 cycles (based on the ability of the cavity-down, injection molded PLCC package (the "J" pack-
compilers to avoid software interlocks). Thus, the execution age). This package, coupled with the power reduction tech-
engineachievesover35MIPSperformancewhenoperating niques employed in the design of the IDT79R3051 family,
out of cache.
allows operation at speeds to 25MHz. However, at higher
speeds, additional thermal care must be taken.
• Large on-chip caches. The IDT79R3051 family contains
caches which are substantially larger than those on the
majorityoftoday’sembeddedmicroprocessors.Theselarge
caches minimize the number of bus transactions required,
and allow the R3051 family to achieve actual sustained
performance, very close to its peak execution rate.
For this reason, the IDT79R3051 family is also available in
the MQUAD package (the "MJ" package), which is an all-
aluminum package with the die attached to a normal copper
lead-frame, mounted to the aluminum casing. The MQUAD
allows for more efficient thermal transfer between the die and
the case of the part due to the heat-spreading effect of the
aluminum. The aluminum offers less internal resistance from
one end of the package to the other, which reduces the
temperature gradient across the package, and, therefore,
presents a greater area for convection and conduction to the
PCB for a given temperature. Even nominal amounts of
airflowwilldramaticallyreducethejunctiontemperatureofthe
die, resulting in cooler operation. The MQUAD package is
available at all frequencies, and is pin- and form-compatible
withthePLCCpackage. Thus, designerscanchoosetoutilize
this package without changing their PCB.
• Autonomous multiply and divide operations. The
IDT79R3051 family features an on-chip integer multiplier/
divideunitwhichisseparatefromtheotherALU. Thisallows
the IDT79R3051 family to perform multiply or divide opera-
tions in parallel with other integer operations, using a single
multiply or divide instruction rather than “step” operations.
• Integrated write buffer. The IDT79R3051 family features a
four-deep write buffer, which captures store target ad-
dressesanddataattheprocessorexecutionrateandretires
it to main memory at the slower main memory access rate.
Use of on-chip write buffers eliminates the need for the
processor to stall when performing store operations.
The members of the IDT79R3051 family are guaranteed in
a case temperature range of 0°C to +85°C. The type of
• Burst read support. The IDT79R3051 family enables the package, speed (power) of the device, and airflow conditions
system designer to utilize page mode or nibble mode RAMs affect the equivalent ambient conditions which meet this
when performing read operations to minimize the main specification.
memory read penalty and increase the effective cache hit
rates.
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(ØCA) of the given package. The following equation relates
ambient and case temperature:
Thesetechniquescombinetoallowtheprocessortoachieve
35MIPS integer performance, and over 64,000 dhrystones at
40MHz without the use of external caches or zero wait-state
memory devices.
TA = TC - P * ØCA
where P is the maximum power consumption at hot tempera-
ture, calculated by using the maximum ICC specification for
the device.
SELECTABLE FEATURES
The IDT79R3051 family allows the system designer to
configure some aspects of operation. These aspects are
established when the device is reset and include:
• Big Endian vs. Little Endian operation: The part can be
configured to operate with either byte ordering convention,
and in fact may also be dynamically switched between the
two conventions. This facilitates the porting of applications
from other processor architectures, and also permits inter-
communications between various types of processors and
databases.
Typical values for ØCA at various airflows are shown in
Table 1 for the various packages.
Airflow (ft/min)
ØCA
0
200
400
600
800
1000
"J" Package
29
26
21
18
16
15
"MJ" Package*
22
14
12
11
9
8
2874 tbl 01
• Data cache refill of one or four words: The memory
system must be capable of performing 4-word transfers to
satisfy cache misses. This option allows the system de-
signer to choose between one- and four-word refill on data
cache misses, depending on the performance each option
brings to his application.
Table 1. Thermal Resistance (ØCA) at Various Airflows
(*estimated: final values tbd)
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
