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IDT71V016SA12PHI8 参数 Datasheet PDF下载

IDT71V016SA12PHI8图片预览
型号: IDT71V016SA12PHI8
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V CMOS静态RAM 1兆欧( 64K ×16位) [3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)]
分类和应用:
文件页数/大小: 9 页 / 102 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
A
4
A
3
A
2
A
1
A
0
CS
I/O
0
I/O
1
I/O
2
I/O
3
V
DD
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-1
SO44-2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
1
A
B
C
D
E
F
G
H
BLE
I/O
8
I/O
9
V
SS
V
DD
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
NC
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
NC
A
15
A
13
A
10
5
A
2
CS
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
DD
V
SS
I/O
6
I/O
7
NC
3834 tbl 02a
FBGA (BF48-1)
Top View
Pin Description
A
0
– A
15
CS
WE
OE
BHE
BLE
I/O
0
– I/O
15
V
DD
V
SS
Address Inputs
Chip Select
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
3.3V Power
Ground
3834 drw 02
Input
Input
Input
Input
Input
Input
I/O
Power
Gnd
3834 tbl 01
SOJ/TSOP
Top View
Truth Table
(1)
CS
H
L
L
L
L
L
L
L
L
OE
X
L
L
L
X
X
X
H
X
WE
X
H
H
H
L
L
L
H
X
BLE
X
L
H
L
L
L
H
X
H
BHE
X
H
L
L
L
H
L
X
H
I/O
0
-I/O
7
High-Z
DATA
OUT
High-Z
DATA
OUT
DATA
IN
DATA
IN
High-Z
High-Z
High-Z
I/O
8
-I/O
15
High-Z
High-Z
DATA
OUT
DATA
OUT
DATA
IN
High-Z
DATA
IN
High-Z
High-Z
Function
Deselected – Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
3834 tbl 02
6.42
2