IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
t
WC
ADDRESS
tAW
CS
(2)
tAS
t
CW
t
BW
BHE, BLE
tWP
tWR
WE
DATAOUT
DATAIN
t
DH
t
DW
DATAIN VALID
3834 drw 09
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
tWC
ADDRESS
tAW
CS
(2)
tCW
tAS
tBW
BHE, BLE
tWP
tWR
WE
DATAOUT
DATAIN
tDH
tDW
DATAIN VALID
3834 drw 10
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WEcontrolled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. Duringthisperiod, I/Opinsareintheoutputstate, andinputsignalsmustnotbeapplied.
4. IftheCSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
6.42
7
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