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IDT7005S15J 参数 Datasheet PDF下载

IDT7005S15J图片预览
型号: IDT7005S15J
PDF下载: 下载PDF文件 查看货源
内容描述: 高速8K ×8双端口静态RAM [HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 20 页 / 265 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT7005S/L  
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
5V 5V  
AC TEST CONDITIONS  
1250  
Input Pulse Levels  
GND to 3.0V  
5ns Max.  
1.5V  
1250Ω  
DATAOUT  
BUSY  
INT  
Input Rise/Fall Times  
Input Timing Reference Levels  
Output Reference Levels  
Output Load  
DATAOUT  
775Ω  
5pF  
775Ω  
30pF  
1.5V  
Figure 1 and 2  
2738 drw 06  
2738 tbl 12  
Figure 2. Output Load  
(For tLZ, tHZ, tWZ, tOW)  
Figure 1. AC Output Test Load  
Including scope and jig  
AC ELECTRICAL CHARACTERISTICS OVER THE  
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)  
IDT7005X15  
Com'l. Only  
Min. Max.  
IDT7005X17  
Com'l. Only  
IDT7005X20  
IDT7005X25  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max. Unit  
READ CYCLE  
tRC  
tAA  
Read Cycle Time  
15  
3
15  
15  
10  
17  
3
17  
17  
10  
10  
17  
17  
20  
3
20  
20  
12  
12  
20  
20  
25  
3
25  
25  
13  
15  
25  
25  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
tACE  
tAOE  
tOH  
tLZ  
Chip Enable Access Time(3)  
Output Enable Access Time  
Output Hold from Address Change  
Output Low-Z Time(1, 2)  
3
3
3
3
tHZ  
Output High-Z Time(1, 2)  
10  
0
0
0
tPU  
Chip Enable to Power Up Time(2)  
Chip Disable to Power Down Time(2)  
Semaphore Flag Update Pulse (OE or SEM)  
Semaphore Address Access Time  
0
tPD  
15  
15  
10  
10  
10  
tSOP  
tSAA  
10  
IDT7005X35  
IDT7005X55  
IDT7005X70  
Mil. Only  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max. Unit  
READ CYCLE  
tRC  
tAA  
Read Cycle Time  
35  
3
35  
35  
20  
15  
35  
35  
55  
3
55  
55  
30  
25  
50  
55  
70  
3
70  
70  
35  
30  
50  
70  
ns  
ns  
Address Access Time  
tACE  
tAOE  
tOH  
tLZ  
Chip Enable Access Time(3)  
Output Enable Access Time  
Output Hold from Address Change  
Output Low-Z Time(1, 2)  
ns  
ns  
ns  
3
3
3
ns  
tHZ  
Output High-Z Time(1, 2)  
0
0
0
ns  
tPU  
Chip Enable to Power Up Time(2)  
Chip Disable to Power Down Time(2)  
Semaphore Flag Update Pulse (OE or SEM)  
Semaphore Address Access Time  
ns  
tPD  
15  
15  
15  
ns  
tSOP  
tSAA  
ns  
ns  
NOTES:  
2738 tbl 13  
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figures 2).  
2. This parameter is guaranteed by device characterization but not production tested.  
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.  
4. "X" in part numbers indicates power rating (S or L).  
6.06  
7