IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
24
23
22
21
20
19
18
17
16
15
14
13
1
B7
B6
B5
B4
B3
B2
B1
Vcc
A7
A6
A5
A4
A3
A2
A1
A0
2
4
3
2
28 27 26
3
5
25
24
23
22
21
20
19
B4
B3
B2
NC
B1
B0
A5
A4
A3
NC
A2
A1
1
P24-1
D24-1
SO24-2
SO24-7*
SO24-8*
&
4
6
5
7
6
8
L28-1
7
9
8
0
B
10
11
E24-1
9
OEB
CPA
CEA
GND
OEB
A0
10
11
12
OEA
CPB
CEB
12 13 14 15 16 17 18
2629 drw 03
2629 drw 02
LCC
TOP VIEW
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
* For 29FCT52/29FCT2052AT/BT/CT only
PIN DESCRIPTION
Name
I/O
I/O
I/O
I
Description
A0-7
Eight bidirectional lines carrying the A Register inputs or B Register outputs.
Eight bidirectional lines carrying the B Register inputs or A Register outputs.
B0-7
CPA
Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of
the CPA signal.
CEA
OEB
CPB
CEB
OEA
I
I
I
I
I
Clock Enable for the A Register. WhenCEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal transitions.
Output Enable for the A Register. When OEB is LOW, the A Register outputs are enabled onto the B0-7 lines. When
OEB is HIGH, the B0-7 outputs are in the high-impedance state.
Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of
the CPB signal.
Clock Enable for the B Register. WhenCEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition
of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal transitions.
Output Enable for the B Register. When OEA is LOW, the B Register outputs are enabled onto the A0-7 lines. When
OEA is HIGH, the A0-7 outputs are in the high-impedance state.
2629 tbl 01
6.1
2
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
