IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
OEB
CPA
CEA
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
P24-1
D24-1
SO24-2
SO24-7*
SO24-8*
&
E24-1
21
20
19
18
17
16
15
14
13
CPA
CEA
GND
NC
CEB
CPB
OEA
Vcc
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
OEA
CPB
CEB
2629 drw 02
B
4
B
3
B
2
NC
B
1
B
0
OEB
B
5
B
6
B
7
NC
Vcc
A
7
A
6
4
5
6
7
8
9
10
3
2
1
28 27 26
25
24
23
L28-1
22
21
20
11
19
12 13 14 15 16 17 18
A
5
A
4
A
3
NC
A
2
A
1
A
0
2629 drw 03
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
* For 29FCT52/29FCT2052AT/BT/CT only
LCC
TOP VIEW
PIN DESCRIPTION
Name
A
0-7
B
0-7
CPA
I/O
I/O
I/O
I
I
I
I
I
I
Description
Eight bidirectional lines carrying the A Register inputs or B Register outputs.
Eight bidirectional lines carrying the B Register inputs or A Register outputs.
Clock for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH transition of
the CPA signal.
Clock Enable for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal. When
CEA
is HIGH, the A Register holds its contents, regardless of CPA signal transitions.
CEA
OEB
CPB
Output Enable for the A Register. When
OEB
is LOW, the A Register outputs are enabled onto the B
0-7
lines. When
OEB
is HIGH, the B
0-7
outputs are in the high-impedance state.
Clock for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH transition of
the CPB signal.
CEB
OEA
Clock Enable for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH transition
of the CPB signal. When
CEB
is HIGH, the B Register holds its contents, regardless of CPB signal transitions.
Output Enable for the B Register. When
OEA
is LOW, the B Register outputs are enabled onto the A
0-7
lines.
OEA
is HIGH, the A
0-7
outputs are in the high-impedance state.
When
2629 tbl 01
6.1
2
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
