ICS511
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin
Number
6
7
8
Pin
Name
S0
OE
X2
Pin
Type
Tri-level Input
Input
Output
Pin Description
Select 0 for output clock. Connect to GND or VDD or float.
Output enable. Tri-states CLK output when low. Internal pull-up
resistor.
Crystal connection. Leave unconnected for clock input.
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS511 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the GND. It must be connected close
to the ICS511 to minimize lead inductance. No external
power supply filtering is required for the ICS511.
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-12 pF)*2. In this equation, C
L
= crystal load capacitance
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 8 pF
[(16-12) x 2] = 8.
Series Termination Resistor
A 33Ω terminating resistor can be used next to the CLK
pin for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include
pads for small capacitors from X1 to ground and from
X2 to ground. These capacitors are used to adjust the
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
3
ICS511
REV K 051310
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
