IDT49FCT806/A
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
7V
5 00
P ulse
G enera to r
V
IN
D .U .T .
50pF
R
T
50 0
C
L
V
OUT
SWITCH POSITION
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
Switch
Closed
GND
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
Test Circuits for All Outputs
3V
1.5 V
IN P U T
t
P L H
t
P H L
V
OH
2.0V
OU TPUT
t
R
0.8V
1.5V
V
OL
OUTPUT 1
t
S K (o )
t
S K (o )
0V
IN P U T
t
P L H 1
t
P L H 1
3V
1 .5V
0V
V
OH
1 .5V
V
OL
V
OH
1 .5V
OUTPUT 2
t
P L H 2
t
P H L 2
or
Package Delay
t
F
V
OL
3V
1.5V
IN P U T
t
P L H
t
P H L
V
OH
1 .5V
OU TPUT
t
S K
(p) = t
P H L
-
t
P L H
V
OL
IN P U T
0V
t
S K
(o ) = t
P L H 2
-
t
P L H 1
t
P H L 2
-
t
P H L 1
Output Skew
3V
1.5V
t
P L H 1
t
P H L 1
0V
V
OH
PACKAGE 1
OUTPUT
1.5V
V
OL
t
S K (p p )
PACKAGE 2
OU TPUT
t
P L H 2
t
S K
(p p) = t
P L H 2
-
t
P L H 1
or
Pulse Skew - t
SK(P)
E N A B LE
C O N TR O L
IN P U T
t
P Z L
O U T PU T
N O R M A LL Y
LO W
O U T PU T
N O R M A LL Y
H IG H
3 .5V
S W IT C H
CLO SED
D IS A B L E
3V
1.5V
0V
3.5V
t
S K (p p )
V
OH
1.5V
V
OL
t
P L Z
t
P H L 2
t
P H L 2
-
t
P H L 1
1.5V
t
P H Z
1.5V
0V
0 .3V V
O L
t
P Z H
S W IT C H
OPEN
0 .3V V
O H
0V
Part-to-Part Skew - t
SK(PP)
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
