IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500Ω
V
IN
Pulse
Generator
R
T
D.U.T.
50pF
C
L
2574 drw 07
ENABLE AND DISABLE TIME
SWITCH POSITION
7.0V
V
OUT
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
Switch
Closed
Open
500Ω
2574 lnk 11
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
PACKAGE DELAY
3V
1.5V
INPUT
t
PLH
t
PHL
V
OH
2.0V
OUTPUT
t
R
t
F
0.8V
1.5V
V
OL
0V
OUTPUT SKEW - t
SK
(o)
INPUT
3V
1.5V
0V
V
OH
1.5V
V
OL
t
SK(o)
OUTPUT 2
t
PLH2
t
PHL2
2574 drw 09
t
PLH1
t
PHL1
OUTPUT 1
t
SK(o)
V
OH
1.5V
V
OL
t
SK(o)
= |t
PLH2 -
t
PLH1
|
or
|t
PHL2 -
t
PHL1
|
2574 drw 08
PULSE SKEW - t
SK
(p)
3V
1.5V
0V
t
PLH
t
PHL
V
OH
1.5V
V
OL
2574 drw 10
PACKAGE SKEW - t
SK
(t)
INPUT
3V
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
t
PLH1
t
PHL1
INPUT
PACKAGE 1 OUTPUT
t
SK(t)
PACKAGE 2 OUTPUT
t
SK(t)
OUTPUT
t
SK(p)
= |t
PHL -
t
PLH
|
t
PLH2
t
PHL2
t
SK(t)
= |t
PLH2 -
t
PLH1
|
or
|t
PHL2 -
t
PHL1
|
Package 1 and Package 2 are same device type and speed grade
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
PZL
2574 drw 11
DISABLE
3V
1.5V
0V
t
PLZ
3.5V
1.5V
t
1.5V
0V
0V
PHZ
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
0.3V V
OL
0.3V V
OH
2574 drw 12
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
9.1
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
