IDT49FCT3805/A
3.3V CMOS BUFFER/CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
6V
SWITCH POSITION
Test
Switch
6V
GND
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
V
CC
GND
500
V
IN
Pulse
Generator
V
OUT
D.U.T.
50pF
R
T
500
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
Test Circuits for All Outputs
3V
1.5V
INPUT
t
PLH
t
PHL
V
OH
2.0V
OUTPUT
t
R
t
F
0.8V
1.5V
V
OL
OUTPUT 2
t
PLH2
t
PHL2
OUTPUT 1
t
SK(o)
t
SK(o)
0V
INPUT
t
PLH1
t
PHL1
3V
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
Package Delay
3V
1.5V
0V
t
PLH
t
PHL
V
OH
1.5V
V
OL
t
SK(o)
= |t
PLH2 -
t
PLH1
|
or
|t
PHL2 -
t
PHL1
|
Output Skew - t
SK(O)
INPUT
INPUT
t
PLH1
PACKAGE 1
OUTPUT
t
SK(t)
PACKAGE 2
OUTPUT
t
PLH2
t
PHL2
t
SK(t)
t
PHL1
3V
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
OUTPUT
t
SK(p)
= |t
PHL -
t
PLH
|
Pulse Skew - t
SK(P)
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
1.5V
0V
0V
3.5V
1.5V
t
PHZ
0.3V V
OH
t
PLZ
3.5V
0.3V V
OL
DISABLE
3V
1.5V
0V
t
SK(t)
= |t
PLH2 -
t
PLH1
|
or
|t
PHL2 -
t
PHL1
|
Package Skew - t
SK(T)
Output Skew - t
SK(X)
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: f
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
