CrystalFree™ Differential Oscillator
Ultra Low Power Oscillators
3LG
PRELIMINARY DATA SHEET
Features
Frequency Range:
Output Type:
Stability:
Supply Voltage:
Power Consumption:
Standby Current:
Standard Package:
24 to 125MHz
LVDS / LVPECL / HCSL
± 50 ppm
2.5V, 3.3V
10.9
mA
(2.5V
LVDS)
< 1 uA
5.0 x 3.2 x 0.85
mm
7.0 x 5.0 x 0.85
mm
0 to 70 °C
Specifications
LVDS
LVPECL
HCSL
LVDS
Specifications
LVPECL
HCSL
LVDS:
LVPECL:
HCSL:
Operating Temperature:
This product is
rated
“Green”,
please
contact factory
for
environmental compliancy information
Specification
Symbol
Parameter
Conditions
100 Ω differential termination
50 Ω termination to VDD-2V
50 Ω termination to GND
Supply Voltage
VDD
2.5 V
3.3 V
F
STB
Frequency Stability
±50
ppm
±50
ppm
IDD
Supply Current
10.9 mA 27.6 mA
22 mA
11.3mA
34.1mA
22.7mA
I
OE
Quiescent Current
1 uA
1 uA
Input LOW
/ HIGH level
V
IL
/ V
IH
0.3VDD
(max)
/ 0.7VDD
(min)
0.3VDD
(max)
/ 0.7VDD
(min)
T
R
/ T
F
500/710ps 620/420ps 580/390ps 450/470ps 430/400ps 420/380ps
Rise
/ Fall Time
V
A
Amplitude
0.35V
0.71V
0.70V
0.35V
0.79V
0.70V
V
M
Mid Level (offset)
1.2 V
1.1V
0.35V
1.2 V
2V
0.35V
SYM
Symmetry
45 / 55%
45 / 55%
Start-up time
Period Jitter
Cycle to Cycle Jitter
Phase Jitter
Output Frequency
T
ST
PJ
RMS
CCJ
Max
φJ
FOUT
3.6 ps
33 ps
400 us
2.9 ps
22 ps
1.0 ps
33.333
Nominal
Total Frequency Stability*
100MHz
Maximum; OE = GND
At OE
pin
Maximum; 20/80% of
V
A
; Output load (CL) =
2pF
Single Ended output swing (Pk-Pk)
Worst case
Output valid time after VDD meets the specified range &
OE
transition
100MHz
100MHz; measured over 12k cycles
12k to 20MHz
(nominal)
125
400 us
2.5 ps
19 ps
2.9 ps
27 ps
3 ps
29 ps
1.0 ps
62.5
66.66
2.6 ps
24 ps
Standard Frequencies:
25
40
50
100
Note: Above specifications are typical at room temperature (25°C ) unless otherwise specified.
* Inclusive of initial frequency accuracy, operating temperature range, supply variation, load variation, 3 times solder reflow, shock, vibration and 10 years aging at 25°C.
Package Outline and Dimensions
5.0 ±0.05
1.30 ±0.05
1.50 ±0.05
Pin #1 ID
R 0.15°
Typical PCB Land Pattern
0.85 ±0.05
0.0-0.05
3.60
OE
5.08
VDD
7.0 x 5.0
(mm)
6L SMD
7.0 x 5.0mm
7.00 ±0.05
2.54 Bsc
0.25 Ref
N/C
GND
0.203 Ref.
1.60
OUTB
OUT
Top View
3.20 ±0.05
Bottom View
1.00 ±0.05
0.64 ±0.05
Pin #1 ID
Chamfer
0.30 x 45°
Side View
0.85 ±0.05
0.0-0.05
1.60
2.60
5.0 x 3.2
(mm)
OE
2.54
VDD
OUTB
OUT
1.50
5.0 x 3.2mm
6L SMD
5.00 ±0.05
1.27 Bsc
1.08 ±0.05
0.203 Ref.
N/C
GND
0.90
Top View
Oct 24, 2011
Bottom View
Side View
©2011 Integrated Device Technology, Inc
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
