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3771G-18LF 参数 Datasheet PDF下载

3771G-18LF图片预览
型号: 3771G-18LF
PDF下载: 下载PDF文件 查看货源
内容描述: [PLL Based Clock Driver, 3771 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 0.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28]
分类和应用: 驱动光电二极管逻辑集成电路
文件页数/大小: 8 页 / 175 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS3771-18
DTV, STB CLOCK SOURCE
SYNTHESIZERS
Pin Assignment
CLKIN
VDD
AVDD
NC
GNDA
GND
REFOUT2
REFOUT1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
OE
FS1
GND
CLK1
VDDL
FS0
CLK2
Output Clock Selection Table (MHz)
OE FS1 FS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CLK1/CLK2
OFF*
OFF*
OFF*
OFF*
27
27.027
74.250
74.17582418
REFOUT1/REFOUT2
27
27
27
27
27
27
27
27
*OFF = output is driven HIGH.
16-pin TSSOP
Pin Descriptions
Pin
Numbe
r
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
CLKIN
VDD
AVDD
NC
GNDA
GND
REFOUT
REFOUT
CLK2
FS0
VDDL
CLK1
GND
FS1
OE
NC
Pin
Type
Input
Power
Power
Power
Power
Output
Output
Output
Input
Power
Output
Power
Input
Output
Pin Description
Reference clock input. Connect to a 27 MHz external clock.
Power supply.
Power supply. Connect to 3.3 V.
No connect. Leave floating.
Analog ground.
Connect to ground.
Reference Clock output 2. See table above.
Reference Clock output 1. See table above.
Selectable Clock output 2. See table above.
Frequency select pin 0. Weak internal pull-up. See table above.
Power supply. Connect to 3.3 V.
Selectable Clock output 1. See table above
Connect to ground.
Frequency select pin 1. Weak internal pull-up. See table above.
Output Enable pin. Weak internal pull-up. See table above.
No connect. Leave floating.
IDT™ / ICS™
DTV, STB CLOCK SOURCE
2
ICS3771-18
REV B 111307