ICS345
Triple PLL Field Programmable SS VersaClock Synthesizer
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Duty Cycle
Power-up time
Symbol
F
IN
Conditions
Fundamental crystal
Input clock
VDD=3.3 V
Min.
5
2
0.25
Typ.
Max. Units
27
50
200
MHz
MHz
MHz
ns
ns
60
10
2
%
ms
ms
t
OR
t
OF
20% to 80%, Note 1
80% to 20%, Note 1
Note 2
PLL lock-time from
power-up, Note 3
PDTS goes high until
stable CLK output,
Spread Spectrum Off,
Note 3
PDTS goes high until
stable CLK output,
Spread Spectrum On,
Note 3
40
1
1
49-51
4
0.2
4
7
ms
One Sigma Clock Period Jitter
Maximum Absolute Jitter
t
ja
Configuration
Dependent
Deviation from Mean.
Configuration
Dependent
Low Skew Outputs
-250
50
+200
ps
ps
Pin-to-Pin Skew
Note 1: Measured with 15pF load
250
ps
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS
transition high on select address change.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
135
93
78
60
Max. Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
MDS 345 E
Integrated Circuit Systems, Inc.
●
6
525 Race Street, San Jose, CA 95126
●
Revision 011205
tel (408) 297-1201
●
www.icst.com
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
