ICS345
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Duty Cycle
Output Frequency Synthesis
Error (Note 4)
Power-up Time
Symbol
F
IN
Conditions
Fundamental crystal
Input clock
VDD=3.3 V
Min.
5
2
0.25
Typ.
Max. Units
27
50
200
MHz
MHz
MHz
ns
ns
60
%
ppm
10
2
ms
ms
t
OR
t
OF
20% to 80%, Note 1
80% to 20%, Note 1
Note 2
Configuration Dependent
PLL lock-time from
power-up, Note 3
PDTS goes high until stable
CLK output, Spread
Spectrum Off, Note 3
PDTS goes high until stable
CLK output, Spread
Spectrum On, Note 3
40
1
1
49-51
0
4
0.2
4
7
ms
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Pin-to-Pin Skew
Note 1:
Measured with 15 pF load.
t
ja
Configuration Dependent
Deviation from Mean.
Configuration Dependent
Low Skew Outputs
-250
50
+200
250
ps
ps
ps
Note 2:
Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
Note 3:
IDT test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS transition
high on select address change.
Note 4:
The actual ppm error will be displayed in the VersaClock software when the programming file is generated
for the customer’s specific configuration. In general, zero ppm error can be achieved, but please note that the
device cannot improve upon the error of the input reference clock. For example, if the input crystal has 25 ppm error,
then the outputs will also have 25 ppm error.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
135
93
78
60
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 6
ICS345
REV K 110207
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
