ICS331-26
Single Output Clock Synthesizer
Pin Assignment
X1/ICLK
VDD
GND
S0
1
2
3
4
8
7
6
5
X2
PDTS
S1
CLK
Output Clock Selection Table
Spread
Percentage
±1.5%
±1.5%
±1.0%
±1.0%
S1
0
0
1
1
S0
0
1
0
0
CLK (MHz)
48
72
48
72
8 pin (150 mil) SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
X1
VDD
GND
S0
CLK
S1
PDTS
X2
Pin
Type
XI
Power
Power
Input
Output
Input
Input
XO
Connect to +3.3 V.
Connect to ground.
Pin Description
Connect this pin to a 24 MHz crystal or clock input.
Select pin 0 for frequency selection on CLK. Internal pull-up.
Clock output per table above. Weak internal pull-down when tri-stated.
Select pin 1 for frequency selection on CLK. Internal pull-up.
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up.
Float for clock input.
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω
.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS331-26 must be isolated from system power supply
noise to perform optimally.
MDS 331-26 E
2
I n t e gra te d D ev i ce Technology, Inc.
●
Revision 051310
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