ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
SER PROG CLOCK SYNTHESIZER
Table 6. Output Divider for Output 2
Divide Value
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
117
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
116
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Bits
115
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
114
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
113
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rule
output divide = ([117..114]+2)*2^[113])
Table 7. Output Divider for Output 3
Divide Value
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
121
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
120
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Bits
119
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
118
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
94
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rule
output divide = ([121..118]+2)*2^[94])
IDT™ / ICS™
SERIALLY PROGRAMMABLE CLOCK SOURCE
6
ICS307-03
REV J 090209