ICS276
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER
EPROM AND VCXO SYNTHESIZER
Parameter
Nom. Output Impedance
Internal pull-up resistor
Internal pull-down
resistor
Input Capacitance
Symbol
Z
O
R
PUS
R
PD
C
IN
Conditions
S2:S0, PDTS
CLK outputs
Inputs
Min.
Typ.
20
190
120
4
Max.
Units
Ω
kΩ
kΩ
pF
Note 1: Example with 25 MHz crystal input, three unloaded 33.3 MHz outputs and VDD = VDDO = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Output Frequency
Crystal Pullability
VCXO Gain
Symbol
F
IN
Conditions
Fundamental crystal
VDDO=VDD
1.8 V<VDDO<2.8
Min.
5
0.314
0.314
100
Typ.
Max. Units
27
200
150
MHz
MHz
MHz
ppm
F
P
0V< VIN < 3.3 V, Note 1,
Config. Dependent
VIN = VDD/2 + 1 V,
Note 1, Config.
Dependent
120
ppm/V
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
t
OF
t
OF
t
OF
80% to 20%, high drive,
Note 2
80% to 20%, low drive,
Note 2
80% to 20%, high drive,
1.8 V<VDDO<2.8
Note 2
Note 3
Configuration Dependent
PLL lock-time from
power-up
PDTS goes high until
stable CLK output
40
1.0
2.0
2.0
ns
ns
ns
Duty Cycle
Output Frequency Synthesis Error
Power-up Time
49-51
TBD
4
0.6
50
+200
60
10
2
%
ppm
ms
ms
ps
ps
One Sigma Clock Period Jitter
Maximum Absolute Jitter
t
ja
Configuration Dependent
Deviation from Mean.
Configuration Dependent
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Note 2: Measured with 15 pF load.
Note 3: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%.
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 6
ICS276
REV D 081809
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
