ICS271
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER
EPROM VCXO AND SYNTHESIZER
Parameter
Power-up time
Symbol
Conditions
PLL lock-time from
power-up
PDTS goes high until
stable CLK output
Min.
Typ.
4
0.6
50
+200
Max. Units
10
2
ms
ms
ps
ps
250
ps
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Pin-to-Pin Skew
t
ja
Configuration Dependent
Deviation from Mean.
Configuration Dependent
Low Skew Outputs
-250
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Note 2: Measured with 15 pF load, VDDO = 3.3 V at VDDO/2.
Note 3: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
93
78
65
20
Max.
Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 7
ICS271
REV D 081809
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
