ICS271
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER
EPROM VCXO AND SYNTHESIZER
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
(CMOS High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Nom. Output Impedance
Internal pull-up Resistor
Internal pull-down
Resistor
Input Capacitance
Symbol
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
Z
O
R
PUS
R
PD
C
IN
ICLK
ICLK
Conditions
Min.
VDD/2+1
Typ.
Max.
VDD/2-1
Units
V
V
V
V
I
OH
= -4 mA
I
OH
= -8 mA (Low Drive);
I
OH
= -12 mA (High Drive)
I
OL
= 8 mA (Low Drive);
I
OL
= 12 mA (High Drive)
Low Drive
High Drive
S2:S0, PDTS
CLK outputs
Inputs
VDD-0.4
2.4
VDDO-0.4
0.4
±40
±70
20
190
120
4
V
mA
Ω
kΩ
kΩ
pF
Note 1: Example with 25 MHz crystal input with six outputs of 33.3 MHz, no load, and VDD = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise,
VDD, VDDO = 3.3 V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Output Frequency
Crystal Pullability
VCXO Gain
Symbol
F
IN
Conditions
Fundamental crystal
VDDO=VDD
1.8V<VDDO<2.8
Min.
5
0.314
0.314
100
Typ.
Max. Units
27
200
150
MHz
MHz
MHz
ppm
F
P
0V< VIN < 3.3 V, Note 1,
Config. Dependent
VIN = VDD/2 + 1 V,
Note 1, Config.
Dependent
120
ppm/V
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
t
OF
t
OF
t
OF
80% to 20%, high drive,
Note 2
80% to 20%, low drive,
Note 2
80% to 20%, high drive,
1.8 V<VDDO<2.8
Note 2
VDDO = 3.3 V, Note 3
Configuration Dependent
40
1.0
2.0
2.0
ns
ns
ns
Output Clock Duty Cycle
Output Frequency Synthesis Error
49-51
TBD
60
%
ppm
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 6
ICS271
REV D 081809
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
