ICS270
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
EPROM VCXO AND SYNTHESIZER
Pin Assignment
VIN
S0
S1
VDD
CLK1
CLK2
CLK3
CLK4
GND
X1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S2
VDD
PDTS
GND
CLK8
CLK7
CLK6
CLK5
VDD
X2
20 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
VIN
S0
S1
VDD
CLK1
CLK2
CLK3
CLK4
GND
X1
X2
VDD
CLK5
CLK6
CLK7
CLK8
GND
PDTS
VDD
S2
Pin
Type
Input
Input
Input
Power
Output
Output
Output
Output
Power
XI
XO
Power
Output
Output
Output
Output
Power
Input
Power
Input
Pin Description
Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO
frequency
Select pin 0. Internal pull-up resistor.
Select pin 1. Internal pull-up resistor.
Connect to +3.3 V.
Output clock 1. Weak internal pull-down when tri-state.
Output clock 2. Weak internal pull-down when tri-state.
Output clock 3. Weak internal pull-down when tri-state.
Output clock 4. Weak internal pull-down when tri-state.
Connect to ground.
Crystal input. Connect this pin to a crystal.
Crystal Output. Connect this pin to a crystal.
Connect to +3.3 V.
Output clock 5. Weak internal pull-down when tri-state.
Output clock 6. Weak internal pull-down when tri-state.
Output clock 7. Weak internal pull-down when tri-state.
Output clock 8. Weak internal pull-down when tri-state.
Connect to ground.
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resisitor.
Connect to +3.3 V.
Select pin 2. Internal pull-up resisitor.
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
2
ICS270
REV D 052008
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
