ICS251 DATASHEET
Pin Assignment
Output Clock Selection Table
S1
S0
CLK (MHz)
Spread
Percentage
User
Configurable
User
Configurable
User
Configurable
User
Configurable
S 0
V D D
1
2
3
4
8
7
6
5
P D T S
G N D
User
Configurable
User
Configurable
User
Configurable
User
Configurable
0
0
1
1
0
1
0
1
X 1 / I C L K
X 2
S 1
C L K
8-pin (150 mil) SOIC
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
2
3
4
5
6
7
S0
VDD
X1/ICLK
X2
Input
Power
XI
Select pin 0 for frequency selection on CLK. Internal pull-up resistor.
Connect to +3.3 V.
Connect this pin to a crystal or external clock input.
Connect this pin to a crystal, or float for clock input.
XO
CLK
S1
Output Clock output. Weak internal pull-down when tri-state.
Input
Select pin 1 for frequency selection on CLK. Internal pull-up resistor.
Connect this to Ground.
GND
Power
Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up
resistor. The pin must be tied either directly or through the external resistor to
VDD or GND. External resistor value must be less than 15kOhm.
8
PDTS
Input
External Components
The ICS251 requires a minimum number of external
components for proper operation.
increased in this trimming process, it is important to keep stray
capacitance to a minimum by using very short PCB traces
(and no vias) been the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to ground.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a commonly
used trace impedance), place a 33 resistor in series with the
clock line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20.
The value (in pF) of these crystal caps should equal (C -6
L
pF)*2. In this equation, C = crystal load capacitance in pF.
L
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS251
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected between
VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for small
capacitors from X1 to ground and from X2 to ground. These
capacitors are used to adjust the stray capacitance of the
board to match the nominally required crystal load
capacitance. Because load capacitance can only be
FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER
2
REVISION E 05/19/14
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
