IDT23S09
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other
outputs that can adjust the Input-Output (I/O) Delay.
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs must be loaded equally.
SWITCHING WAVEFORMS
t1
t2
1.4V
1.4V
1.4V
Output
Output
1.4V
1.4V
t5
Duty Cycle Timing
Output to Output Skew
Output
0.8V
t3
2V
2V
0.8V
t4
3.3V
0V
REF
Output
t6
V
DD/
2
V
DD/
2
All Outputs Rise/Fall Time
Input to Output Propagation Delay
CLKOUT
Device 1
CLKOUT
Device 2
t7
V
DD
/2
V
DD
/2
Device to Device Skew
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
