23S08E-1HDCGI8 参数 Datasheet PDF下载

IDT23S08E

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FUNCTION TABLE

(1)

SELECT INPUT DECODING

S2

L

L

H

H

NOTE:

1. H = HIGH Voltage Level

L = LOW Voltage Level

S1

L

H

L

H

CLK A

Tri-State

Driven

Driven

Driven

CLK B

Tri-State

Tri-State

Driven

Driven

Output Source

PLL

PLL

REF

PLL

PLL Shut Down

Y

N

Y

N

AVAILABLE OPTIONS FOR IDT23S08

Device

IDT23S08E-1

IDT23S08E-1H

IDT23S08E-2

IDT23S08E-2

IDT23S08E-2H

(1)

IDT23S08E-2H

(1)

IDT23S08E-3

(1)

IDT23S08E-3

(1)

IDT23S08E-4

IDT23S08E-5H

Feedback From

Bank A or Bank B

Bank A or Bank B

Bank A

Bank B

Bank A

Bank B

Bank A

Bank B

Bank A or Bank B

Bank A or Bank B

Bank A Frequency

Reference

Reference

Reference

2 x Reference

Reference

2 x Reference

2 x Reference

4 x Reference

2 x Reference

Reference/2

Bank B Frequency

Reference

Reference

Reference/2

Reference

Reference/2

Reference

Reference or

Reference

(2)

2 x Reference

2 x Reference

Reference/2

NOTES:

1. Contact factory for availability.

2. Output phase is indeterminant (0° or 180° from input clock).

SPREAD SPECTRUM COMPATIBLE

Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter

off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature

through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.

3