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23S05T-1DCG 参数 Datasheet PDF下载

23S05T-1DCG图片预览
型号: 23S05T-1DCG
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5V零延迟时钟缓冲器,扩频兼容 [2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE]
分类和应用: 时钟驱动器逻辑集成电路光电二极管PC
文件页数/大小: 6 页 / 54 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT23S05T
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V ZERO DELAY CLOCK
BUFFER, SPREAD SPECTRUM
COMPATIBLE
FEATURES:
Phase-Lock Loop Clock Distribution
10MHz to 133MHz operating frequency
Distributes one clock input to one bank of five outputs
Zero Input-Output Delay
Output Skew < 250ps
Low jitter <200 ps cycle-to-cycle
No external RC network required
Operates at 2.5V V
DD
Power down mode
Spread spectrum compatible
Available in SOIC package
IDT23S05T
DESCRIPTION:
The IDT23S05T is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT23S05T is an 8-pin version of the IDT23S09T. IDT23S05T
accepts one reference input, and drives out five low skew clocks. All parts
have on-chip PLLs which lock to an input clock on the REF pin. The PLL
feedback is on-chip and is obtained from the CLKOUT pad. In the absence
of an input clock, the IDT23S05T enters power down. In this mode, the
device will draw less than 12µA for Commercial Temperature Range and
and less than 25µA for Industrial temperature range, the outputs are tri-
stated, and the PLL is not running, resulting in a significant reduction of
power. The IDT23S05T is characterized for both Industrial and Commer-
cial operation.
FUNCTIONAL BLOCK DIAGRAM
8
CLKOUT
REF
1
PLL
Control
Logic
3
CLK1
2
CLK2
5
7
CLK3
CLK4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2006
Integrated Device Technology, Inc.
MAY 2010
DSC 6397/11